1. Field of the Invention
The present invention relates to a memory circuit, and more particularly, to on-die termination operation of a memory circuit.
2. Description of the Related Art
During propagation on a transmission line, electrical signals are reflected when an end of the transmission line is reached. This signal reflection causes noise and hence reduces the signal integrity. In low frequency applications, the transmission lines and the interconnection between lines can be considered as a lumped circuit, and thus this signal reflection can be ignored. However, in high frequency applications, where signal integrity is critical, the signal reflection problem becomes severe. Accordingly, an impedance mismatch of the transmission line, or a termination of the electrical signal, can be utilized to reduce the signal reflection. There are several signal termination techniques that can be utilized. Among these signal termination techniques, the on-die termination (ODT) technique is often utilized in memory circuits.
ODT allows the termination resistors for impedance matching in the transmission line to be located inside a circuit chip rather than on a printed circuit board. Therefore, ODT technique exhibits advantages such as reduced use of board space due to the elimination of the external resistors and the improving of the signal integrity by having the termination closer to the input of the memory device.
The operation of ODT is controlled by the ODT signal provided by a memory circuit. FIG. 1 shows a block diagram of a conventional memory circuit. As shown in FIG. 1, the memory circuit 100 comprises a delay locked loop (DLL) module 101, a clock driver 102, an ODT counter 103 and a plurality of input/output (I/O) buffers 104. The DLL module 101 is configured to provide a root clock signal based on an external clock signal received via a clock input buffer 150. The clock driver 102 is configured to provide a system clock signal based on the root clock signal to the plurality of I/O buffers 104 through a clock tree 120. The ODT counter 103 is configured to provide a system ODT signal based on an external ODT signal received via an ODT input buffer 160 and the root clock signal to the plurality of I/O buffers 104 through an ODT tree 130.
FIG. 2 shows the signal waveforms of the memory circuit 100 shown in FIG. 1 during the ODT operation. As shown in FIG. 2, an external clock signal and an external ODT signal are provided to the memory circuit 100. The root clock signal is generated based on the external clock signal. The system clock signal is generated based on the root clock signal. The system ODT signal is generated based on the root clock signal and the external ODT signal. At the leaves of the clock tree 120, each of the I/O buffers receives both the system clock signal and the system ODT signal, wherein the system clock signal is used to control the timing by allowing the system ODT signal to pass or not. That is, the final ODT timing information is generated locally at each of the plurality of I/O buffers 104. As shown in FIG. 2, the system clock signal on the clock tree 120 continuously toggles during the ODT operation and thus the memory circuit 100 consumes a lot of power, which is undesirable for the memory circuit application.